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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
Programmable Timing Control HubTM for P4TM
Recommended Application: ALI 1671/1672 P4 Chipset
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 CLK_STOPB GND GND DDRT0 DDRC0 GND VDDL DDRT1 DDRC1 DDRT2 DDRC2 VDDL GND DDRT3 DDRC3 DDRT4 DDRC4 GND VDDL DDRT5 DDRC5 PWRGD_PDB SCL
AVCO_CORE X1 X2 Output Features: GND * 2 - Pairs of differential CPU clocks (differential current mode) VDD 50M/REF_SEL_REF0 * 2 - AGP @ 3.3V REF1 * 7 - PCI @ 3.3V VDD * 1 - 48MHz @ 3.3V fixed FS0_REF2 REF3_PLL_50 * 1 - REF @ 3.3V, 14.318MHz GND * 7 - Pairs of differential SSTL2 DDR @ 2.5V FS1/PCICLK0 FS2/PCICLK9 Features/Benefits: SSEN_PCICLK1 PCICLK2 * Programmable output frequency. GND * Programmable output divider ratios. VDD PCICLK3 * Programmable output rise/fall time. PCICLK4 * Programmable output skew. PCICLK5 PCI_STOPB * Programmable spread percentage for EMI control. SDA * Watchdog timer technology to reset system VDD if system malfunctions. FS3/AGP0 GND * Programmable watch dog safe frequency. AGP1 * Support I2C Index read/write and block read/write operations. AGP2 * Uses external 14.318MHz crystal. AGP3
Key Specifications: * CPU Output Jitter <150ps * AGP Output Jitter <250ps * DDR Output Jitter <250ps * CPU - DDR Skew <250ps * CPU - AGP/PCI Skew = 2.5ns 500ps
56-Pin 300-mil SSOP, 240-mil TSSOP
1 These outputs have 2x drive strength * Internal Pull-up resistor of 120K to VDD ** These inputs have 120K internal pull-down to GND
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 66.66 66.66 100.00 100.00 100.00 133.33 133.33 133.33 66.66 66.66 100.00 100.00 100.00 133.33 133.33 133.33 DDR 66.66 100.00 66.66 100.00 133.33 66.66 100.00 133.33 66.66 100.00 66.66 100.00 133.33 66.66 100.00 133.33 AGP 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66
Block Diagram
PLL2 48MHz
X1 X2
XTAL OSC PLL1 Spread Spectrum
REF0
CPU DIVDER
Stop
2 2
CPUCLKT (1:0) CPUCLKC (1:0) PCICLK (5:0) PCICLK_E
PCI DIVDER
Stop
7
PD# MULTSEL FS (3:0) SDATA SCLK Vtt_PWRGD CLK_STOP# PCI_STOP#
Control Logic
AGP DIVDER DDR DIVDER Stop
2 7 7
AGP (1:0) DDRC (6:0) DDRT (6:0) RESET# I REF
Config. Reg.
Stop
Host Swing Select Functions
MULTISEL0 Board Target Trace/Term Z 50 ohms 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4* I REF Ioh = 6* I REF Voh @ Z
0 1
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1.0V @ 50 0.7V @ 50
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
General Description
The ICS951104 is a single chip clock solution for desktop designs using the ALI 1671/1672 P4 Chipset. It provides all necessary clock signals for such a system. The ICS951104 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
P IN NUM BE R 1 5, 8, 17, 54 2 3 P IN NAM E AVDD_CO RE VDD X1 X2 T YPE PW R PW R IN O UT PW R IN O UT O UT IN OUT OUT OUT IN IN O UT O UT IN IN IN PW R IN O UT IN I/O IN O UT O UT PW R O UT O UT O UT Analog cor e supply 3. 3V 3. 3V pow er supply. Cr yst al input , has int er nal load cap ( 33pF) and f eedback r esist or f r om X2. Cr yst al out put , nominally 14. 318M Hz. Has int er nal load cap ( 33pF) . G r ound pins f or 3. 3V supply. 3.3V LVTTL input for selecting the current multiplier for CPU outputs 3. 3V, 14. 318M Hz r ef er ence clock out put . Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. Logic input f r equency select bit . I nput lat ched at pow er on. 3. 3V clock out put s 3. 3V clock out put s 3. 3V Ear ly PCI clock out put . Logic input f r equency select bit . I nput lat ched at pow er on. Logic input f r equency select bit . I nput lat ched at pow er on. 3. 3V PCI clock out put . 3. 3V PCI clock out put s. St ops all PCI CLKs at logic 0 level, w hen input low besides t he PCI CLK_F clocks w hich ar e cont r ollable by I 2C bit s w het her t hey ar e f r ee r unning or st opped by PCI _STO P. This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (3:0) inputs are valid and are ready to be sampled (active high). Asynchr onous act ive low input pin used t o pow er dow n t he device int o a low pow er st at e. The int er nal clocks ar e disabled and t he VCO and t he cr yst al ar e st opped. The lat ency of t he pow er dow n w ill not be gr eat er t han 3ms. Analog pow er f or 48M Hz out put 3. 3V. Logic input f r equency select bit . I nput lat ched at pow er on. 3. 3V Fixed 48M Hz clock out put Data pin for I2C circuitry 5V tolerant. Clock pin for I2C circuitry 5V tolerant. This asynchronous input halts CPU, AGP or DDR clocks at logic "0" level when driven low. These stops are configurable via IIC. "Complementory" clocks of differential pair DDRC outputs. "True" clocks of differential pair DDRT outputs. Power supply for 2.5V This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "Complementory" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. DE S CRIP T IO N
4, 11, 16, 25, 34, 39, G ND 46, 49, 50 MULTSEL 6 REF0 7 9 10 12 FS1 13 20 , 19, 18, 15, 14 21 FS2 PCI CLK0 PCI CLK ( 5: 1) PCI _STO P# Vtt_PWRGD 22 PD# 23 24 48M Hz 26 27 28 SDATA SCLK CLK_STOP# DDRC (6:0) DDRT (6:0) VDDL I REF CPUCLKT (1:0) CPUCLKC (1:0) AVDD48 F S3 RESET# FS0 AGP0 AGP1 PCICLK_E
o
29, 31, 35, 37, 41, 43, 47 30, 32, 36, 38, 42, 44, 48 33, 40, 45 51 53, 56 52, 55
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview General I2C serial interface information
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description Spread Precentage +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread Spread Off +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread
PWD
FS3 FS2 FS1 FS0 CPUCLK DDR AGP PCICLK (MHz) (MHz) (MHz) (MHz) Bit2 Bit7 Bit6 Bit5 Bit4 0 0 0 0 0 66.66 66.66 66.66 33.33 0 0 0 0 1 66.66 100.00 66.66 33.33 0 0 0 1 0 100.00 66.66 66.66 33.33 0 0 0 1 1 100.00 100.00 66.66 33.33 0 0 1 0 0 100.00 133.33 66.66 33.33 0 0 1 0 1 133.33 66.66 66.66 33.33 0 0 1 1 0 133.33 100.00 66.66 33.33 0 0 1 1 1 133.33 133.33 66.66 33.33 0 1 0 0 0 66.66 66.66 66.66 33.33 0 1 0 0 1 66.66 100.00 66.66 33.33 0 1 0 1 0 100.00 66.66 66.66 33.33 0 1 0 1 1 100.00 100.00 66.66 33.33 0 1 1 0 0 100.00 133.33 66.66 33.33 0 1 1 0 1 133.33 66.66 66.66 33.33 0 1 1 1 0 133.33 100.00 66.66 33.33 Bit 2, Bit 7:4 0 1 1 1 1 133.33 133.33 66.66 33.33 1 0 0 0 0 70.00 70.00 70.00 35.00 1 0 0 0 1 100.00 166.67 62.50 31.25 1 0 0 1 0 105.00 70.00 70.00 35.00 1 0 0 1 1 105.00 105.00 70.00 35.00 1 0 1 0 0 105.00 140.00 70.00 35.00 1 0 1 0 1 100.00 166.67 71.43 35.72 1 0 1 1 0 140.00 105.00 70.00 35.00 1 0 1 1 1 140.00 140.00 70.00 35.00 1 1 0 0 0 133.30 166.60 33.33 66.65 1 1 0 0 1 73.33 110.00 73.33 36.66 1 1 0 1 0 110.00 73.33 73.33 36.66 1 1 0 1 1 110.00 110.00 73.33 36.66 1 1 1 0 0 110.00 146.66 73.33 36.66 1 1 1 0 1 146.66 73.33 73.33 36.66 1 1 1 1 0 146.66 110.00 73.33 36.66 1 1 1 1 1 146.66 146.66 73.33 36.66 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 2, 7:4 Bit 1 0 - Normal 1 - Spread Spectrum Enabled 0 - Running Bit 0 1- Tristate all outputs
00000 Note1
0 0 0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
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ICS951104 Preliminary Product Preview
Byte 1: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 53, 52 56, 55 20 PWD X 1 1 1 X X X X Description MULT_SEL (readback) CPUT/C1 CPUT/C0 PCICLK_5 drive strength control 1 = 2X , 0 = 1X FS3 Read back FS2 Read back FS1 Read back FS0 Read back
Byte 2: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 12 20 19 18 15 14 13
PWD 1 1 1 1 1 1 1
Description PCICLK_E PCICLK_5 PCICLK_4 PCICLK_3 PCICLK_2 PCICLK_1 PCICLK_0
Byte 3: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 24 48, 47 42, 41, 44, 43 36, 35, 38, 37 30, 29, 32, 31 10 9 PWD 1 1 1 1 1 1 1 1 Description 48MHZ DDRT/C0 Reset gear shift detect 1 = Enable, 0 = Disable DDRT/C (2:1) DDRT/C (4:3) DDRT/C (6:5) AGP1 AGP0
Byte 4: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Pin# -
PWD 0 0 0 0 0 0 0 0
Description CPUT/C0 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable CPUT/C1 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable AGP0 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable AGP1 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable DDRT/C(6:0) Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable DDRT/C0 Stop via CLK_STOP enable bit, 0 = Free Run; 1 = Stoppable CPUCLKT1 PD# STOP polarity control, 0 = Stop High; 1 = Stop Low CPUCLKT0 PD# STOP polarity control, 0 = Stop High; 1 = Stop Low
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
Byte 5: Programming Edge Rate (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# X X X X X X X
PWD 0 0 0 0 0 0 0
Description PCICLK_E STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable PCICLK5 STOP via PCI_STOP enable bit, 0 = Free Run; 1 = Stoppable PCICLK4 STOP via PCI_STOP enable bit, PCICLK3 STOP via PCI_STOP enable bit, PCICLK2 STOP via PCI_STOP enable bit, PCICLK1 STOP via PCI_STOP enable bit, PCICLK0 STOP via PCI_STOP enable bit, 0= 0= 0= 0= 0= Free Run; Free Run; Free Run; Free Run; Free Run; 1= 1= 1= 1= 1= Stoppable Stoppable Stoppable Stoppable Stoppable
Byte 6: Vendor ID Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0 PWD X X X X 0 0 0 1 Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved)
Byte 7: Revision ID and Device ID Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Device ID7 Device ID6 Device ID5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0
PWD Description 0 0 1 Device ID values will be based on individual device 0 "22H" in this case. 0 0 1 0
Byte 8: Byte Count Read Back Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure byte count and how 0 many bytes will be read back, default is 0FH = 15 bytes. 1 1 1 1
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ICS951104 Preliminary Product Preview
Byte 9: Watchdog Timer Count Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD Description 0 0 0 The decimal representation of these 8 bits correspond to X * 0 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 1 8 * 290ms = 2.3 seconds. 0 0 0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Program Enable WD Enable WD Alarm S F4 S F3 S F2 S F1 S F0
PWD 0 0 0 0 0 0 0 0
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X
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ICS951104 Preliminary Product Preview
Byte 13: Spread Spectrum Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD X X X X X X X X
Description The Spread Spectrum (12:0) (or, see Byte 14) bit will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name DDRC Div 3 DDRC Div 2 DDRC Div 1 DDRC Div 0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD X X X X X X X X
Description DDRC clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPUCLK1 clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name DDRT Div 3 DDRT Div 2 DDRT Div 1 DDRT Div 0 AGP Div 3 AGP Div 2 AGP Div 1 AGP Div 0
PWD X X X X X X X X
Description DDRT clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
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ICS951104 Preliminary Product Preview
Byte 17: Output Divider Control Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCI_INV 3V66_INV Reserved CPU_INV PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0 PWD X X X X X X X X Description PCICLK Phase Inversion bit 3V66 Phase Inversion bit Reserved CPUCLK Phase Inversion bit PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider.
Table 1
Div (3:2) Div (1:0) 00 01 10 11 00 /2 /3 /5 /7 01 /4 /6 /10 /14 10 /8 /12 /20 /28 11 /16 /24 /40 /56
Table 2
Div (3:2) Div (1:0) 00 01 10 11 00 /4 /3 /5 /9 01 /8 /6 /10 /18 10 /16 /12 /20 /36 11 /32 /24 /40 /72
Byte 18: Group Skew Control Register
Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 Name These 4bits control CPU-DDRC (6:0) PWD 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1 Programming Sequence 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps Reserved Reserved Reserved Reserved Reserved Reserved
Bit 1 Bit 0
These 4 bits control all clocks to CPUT/C (1:0)
1 1 1 1 900ps Reserved Reserved Reserved
Byte 19: Group Skew Control Register
Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 Name These 4bits control CPU-DDRT (6:0) PWD 0 0 0 0 1 1 0 1 0 0 1 1 1 1 CPU-DDR 0 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 CPU-AGP 1.85ns 2.00ns 2.15ns 2.30ns 2.45ns 2.60ns 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 3.05ns 3.20ns 3.35ns 3.50ns 3.65ns 3.80ns
Bit 1 Bit 0
These 4 bits control CPU-AGP(1:0)
1 1 1 1 900ps 0 1 1 0 2.75ns 1 1 1 0 3.95ns Reserved 0 1 1 1 2.90ns 1 1 1 1 4.10ns
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ICS951104 Preliminary Product Preview
Byte 20: Group Skew Control Register
Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 Name These 4bits control CPU-PCI(6:0) PWD 0 0 0 0 1 0 0 0 0 0 1 1 1 1 CPU-PCI_E 0 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0ps 150ps 300ps 450ps 600ps 750ps 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 CPU-PCI 1.85ns 2.00ns 2.15ns 2.30ns 2.45ns 2.60ns 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 3.05ns 3.20ns 3.35ns 3.50ns 3.65ns 3.80ns
Bit 1 Bit 0
These 4 bits control CPU-PCI_E
1 1 1 1 900ps 0 1 1 0 2.75ns 1 1 1 0 3.95ns Reserved 0 1 1 1 2.90ns 1 1 1 1 4.10ns
Byte 21: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name REF0 REF0 Reserved AGP(1:0) Reserved PWD Strength Select 1 Clock slew rate control bits. 01 = strong: 11 = 00 medium: 10 = weak 0 Select 1 1X = 1: 2X = 0 X Reserved 1 Clock slew rate control bits. 01 = strong: 11 = 00 medium: 10 = weak 0 X Reserved X
Byte 22: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name PCI_E PCI5 PCI(4:2) PCI(1:0)
PWD 1 0 1 0 1 0 1 0
Strength Select Clock slew rate control bits. 01 = strong: 11 = 00 medium: 10 = weak Clock slew rate control bits. 01 = strong: 11 = 00 medium: 10 = weak Clock slew rate control bits. 01 = strong: 11 = 00 medium: 10 = weak Clock slew rate control bits. 01 = strong: 11 = 00 medium: 10 = weak
Byte 23: Slew Rate Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Reserved Reserved Reserved 48MHz
PWD X X X X X X 1 0
Strength Select Reserved Reserved Reserved Clock slew rate control bits. 01 = strong: 11 = 00 medium: 10 = weak
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ICS951104 Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance 1 Transition Time1 Settling Time 1 Clk Stabilization 1 Delay
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi L pin C IN Cout C INX Ttrans Ts TSTAB tPZH,tPZH tPLZ,tPZH VIN = VDD
CONDITIONS
MIN 2 VSS-0.3 -5 -5 -200
TYP
MAX UNITS VDD+0.3 V 0.8 5 V mA mA 100 280 20 37 7 5 6 mA mA mA mA mA MHz nH pF pF pF mS mS mS nS nS
VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = Full load IREF=2.32 IREF= 5mA VDD = 3.3 V; Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
27
45 3 3 3 10 10
1 1
Guarenteed by design, not 100% tested in production.
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ICS951104 Preliminary Product Preview
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70 C; VDD = 3.3 V +/-5%; (unless otherwise stated) PARAMETER Current Source Output Impedance Output High Voltage Output High Current Rise Time1 Differential Crossover Voltage Duty Cycle1 Skew 1, CPU to CPU Jitter, Cycle-to-cycle1
1
SYMBOL ZO VOH IOH tr VX dt tsk tjcyc-cyc VO = VX
CONDITIONS
MIN 3000
TYP
MAX
UNITS W
0.71 VR = 475W +1%; IREF = 2.32mA; IOH = 6*IREF -13.9 VOL = 20%, VOH = 80% Note 3 VT = 50% VT = 50% VT = VX 175 45 45 50 51
1.2
V mA
600 55 55 100 150
ps % % ps ps
Notes: 1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter PCI (5:0) Jitter PCI_E Skew PCI_E-PCI (5:0)
1
SYMBOL F01 R DSN11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 tjcyc-cyc1 tCYC-CYC tSK VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA
CONDITIONS
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33.33
MAX 55 0.55 -33 38 2.5 2.5 55 150 350 200
UNITS MHz W V V mA mA ns ns % ps ps ps ns
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5V VT = 1.5V
1
3.2
3.5
Guarenteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
Electrical Characteristics - DDRT/C
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter Skew1 SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 Tf3
1 1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V 20-80 80-20 VT = 1.5 V VT VT = 1.5 V
MIN 2.4
TYP
MAX 0.4 -54
41 450 450 45 1200 1200 55 150 150
UNITS V V mA mA ps ps % ps ps
Dt3
Tsk1
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 R DSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 VO = VDD*(0.5) IOH = -1 mA
CONDITIONS
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 66.66
MAX 55 0.4 -33 38 2 2 55 100 450
UNITS MHz W V V mA mA ns ns % ps ps
IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V
VT = 1.5 V tjcyc-cyc1 VT = 1.5 V
Guarenteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; C L = 10-30 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current VCH 48 USB Rise Time VCH 48 USB Fall Time Duty Cycle Jitter
1
SYMBOL FO1 R DSN11 VOH1 VOL1 IOH1 IOL1 tr
1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -29 29
TYP 48
MAX 55 0.55 -23 27 1.5 1.5
UNITS MHz W V V mA mA ns ns % ps
tf1 d t11 tjcyc-cyc1
45
55 350
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL FO1 RDSP11 V OH1 V OL1 I OH1 IOL1 t r11 t f11 dt11 t jcyc-cyc
1
CONDITIONS VO = V DD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29
TYP
MAX UNITS MHz 60 0.4 -23 27 2 2 W V V mA mA ns ns % ps
45
55 1000
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms
PCI_STOP# Tsu 10ns min PCI_F PCI
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUCLKT CPUCLKC
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
CPU_STOP# - De-assertion (transition from logic "0" to logic "1") All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the deassertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 3 nS of CPU_Stop# de-assertion.
De-assertion of CPU_STOP# Waveforms
CPU_STOP# CPUCLKT(2:0) Tdrive_CPU_STOP# <10ns @ 200mV *CPUCLKT(2:0)TS CPUCLKC(2:0) *Signal TS is CPUCLKT in Tri-State mode
PD# - Assertion (transition from logic "1" to logic "0") When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power Down Assertion of Waveforms
2 CPU Clock Latency CPUCLKT CPUCLKC DDRT DDRC AGP PCI 48MHz PD#
1.8ms Typical
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ICS951104 Preliminary Product Preview
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS951104yFT
Example:
ICS XXXXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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Integrated Circuit Systems, Inc.
ICS951104 Preliminary Product Preview
N
c
L
SYMBOL A A1 A2 b c D E E1 e L N aaa
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.10 -.004
-Ce
b SEATING PLANE
VARIATIONS N 56
10-0039
D mm. MIN 13.90 MAX 14.10 MIN .547
D (inch) MAX .555
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil)
Ordering Information
ICS951104yGT
Example:
ICS XXXXXX y G - T
Designation for tape and reel packaging Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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